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| -1 - 02/03/18 NJU6674 38-common x 132-segment+1-icon common bitmap lcd driver general description the NJU6674 is a bitmap lcd driver to display graphics or characters. it contains 5,148 bits display data ram, microprocessor interface circuits, instruction decoder, 38-common and 132-segment +1-icon common drivers. the bit image display data is transferred to the display data ram by serial or 8-bit parallel interface. 39 x 132 dots graphics or 10-character 3-line by 12 x 13 dot character with icon are displayed by NJU6674 itself. the wide operating voltage from 2.4v to 3.3v and low operating current are suitable for small sized battery operated items. features direct correspondence between display data ram and lcd pixel display data ram : 5,148-bit lcd drivers : 132-seg, 38-com+1-icon com bias select 1/5 bias or 1/6 bias direct interface with 68 and 80 type mpu serial interface (si, scl, a0, cs 1 b, cs 2 ) useful instruction set display on/off ,display start line set, page address set, column address set, status read, display data write, display data read, adc select, inverse display, entire display on/off, bias select, read modify write, end, reset, power control set, internal resistor ratio set, evr register set, evr mode set, power saving power supply circuits for lcd incorporated step up circuit (x2, x3, x4), regulator, voltage follower x4, v 5 level is adjusted by internal bleeder resistanceprecision electrical variable resistance (64-steps) bias stabilization capacitor less low power consumption operating voltage (all the voltages are based on v dd =0v.) ? logic operating -2.4 to -3.3v ? voltage booster operating voltage -2.4 to -3.3 v ? lcd driving voltage -5.0 to -10.0v rectangle outlook for cog package outline: bump-chip/tcp/cof c-mos technology (substrate: n) preliminary package NJU6674cj
- 2 - NJU6674 pad location chip center :x=0 m,y=0 m chip size :x=10.38mm, y= 2.51mm chip thickness :400 m 30 m bump size :78.16 m x 48.10 m pad pitch :72 m(min) bump height :17.5 m(typ) bump material :au voltage boosting polarit y :negative voltage(v dd common) substrate :n cs2 v ss1 v out d 4 d 3 d 5 d 7 (si) d 6 (scl) v dd v dd v dd v ss1 v dd v ss1 v ss2 v ss1 v ss2 v ss2 v out c 3 - c 3 - c 1 + c 1 + c 1 - c 2 - c 1 - c 2 - c 2 + c 2 + v ss1 v rs v ss1 v rs v dd v dd v 1 v 2 v 1 v 2 v 3 v 3 v 4 v 4 v 5 v 5 vr v dd vr v dd test cls sel68 v ss1 p/s v ss1 v dd y x s 131 s 1 s 0 c 18 dummy 3 1 a0 resb v ss1 rd(e) wrb(r/wb) v dd d 1 d 0 d 2 cs1b v dd cl irs dummy 15 c 37 dummy 32 c 19 coms c 0 s 130 coms dummy 17 v dd dummy 1 v ss2 v dd dummy 16 dummy 25 dummy 26 dummy 38 ali_b2 ali_b1 ali_a2 a li_a1 110.34 ? alignment marks note) alignment marks are not contains window. -3 - NJU6674 pad coordinates chip size 10.38x2.51mm(chip center x=0 m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= m y= m 1 dummy 1 -4949 -1098 51 c1+ 442 -1098 2 dummy 2 -4877 -1098 52 c1- 514 -1098 3 dummy 3 -4805 -1098 53 c1- 586 -1098 4 dummy 4 -4733 -1098 54 c2- 658 -1098 5 dummy 5 -4661 -1098 55 c2- 730 -1098 6 dummy 6 -4589 -1098 56 c2+ 802 -1098 7 dummy 7 -4517 -1098 57 c2+ 874 -1098 8 dummy 8 -4445 -1098 58 v ss1 946 -1098 9 dummy 9 -4373 -1098 59 v ss1 1018 -1098 10 dummy 10 -4301 -1098 60 v rs 1090 -1098 11 dummy 11 -4229 -1098 61 v rs 1162 -1098 12 dummy 12 -4157 -1098 62 v dd 1234 -1098 13 dummy 13 -4085 -1098 63 v dd 1306 -1098 14 dummy 14 -4013 -1098 64 v 1 1378 -1098 15 dummy 15 -3941 -1098 65 v 1 1450 -1098 16 cl -3869 -1098 66 v 2 1522 -1098 17 v ss1 -3797 -1098 67 v 2 1594 -1098 18 cs1b -3725 -1098 68 v 3 1666 -1098 19 cs2 -3653 -1098 69 v 3 1738 -1098 20 v dd -3581 -1098 70 v 4 1810 -1098 21 resb -3509 -1098 71 v 4 1882 -1098 22 a0 -3437 -1098 72 v 5 1954 -1098 23 v ss1 -3365 -1098 73 v 5 2026 -1098 24 wrb -3293 -1098 74 vr 2098 -1098 25 rdb -3221 -1098 75 vr 2170 -1098 26 v dd -3149 -1098 76 v dd 2242 -1098 27 d 0 -2879 -1098 77 v dd 2314 -1098 28 d 1 -2599 -1098 78 test 2386 -1098 29 d 2 -2319 -1098 79 v dd 2458 -1098 30 d 3 -2039 -1098 80 cls 2530 -1098 31 d 4 -1759 -1098 81 v ss1 2602 -1098 32 d 5 -1479 -1098 82 sel68 2674 -1098 33 d 6 (scl) -1199 -1098 83 p/s 2746 -1098 34 d 7 (si) -919 -1098 84 v dd 2818 -1098 35 v dd -710 -1098 85 dummy 16 2890 -1098 36 v dd -638 -1098 86 v ss1 2962 -1098 37 v dd -566 -1098 87 irs 3034 -1098 38 v dd -494 -1098 88 v dd 3106 -1098 39 v ss1 -422 -1098 89 dummy 17 3178 -1098 40 v ss1 -350 -1098 90 dummy 18 3250 -1098 41 v ss1 -278 -1098 91 dummy 19 3322 -1098 42 v ss2 -206 -1098 92 dummy 20 3394 -1098 43 v ss2 -134 -1098 93 dummy 21 3466 -1098 44 v ss2 -62 -1098 94 dummy 22 3538 -1098 45 v ss2 10 -1098 95 dummy 23 3610 -1098 46 v out 82 -1098 96 dummy 24 3682 -1098 47 v out 154 -1098 97 dummy 25 3754 -1098 48 c3- 226 -1098 98 ali_a2 5036 -1098 49 c3- 298 -1098 99 c 18 5036 -943 50 c1+ 370 -1098 100 c 17 5036 -871 - 4 - NJU6674 pad no. terminal x= m y= m pad no. terminal x= m y= m 101 c 16 5036 -799 151 s 25 2916 1098 102 c 15 5036 -727 152 s 26 2844 1098 103 c 14 5036 -655 153 s 27 2772 1098 104 c 13 5036 -583 154 s 28 2700 1098 105 c 12 5036 -511 155 s 29 2628 1098 106 c 11 5036 -439 156 s 30 2556 1098 107 c 10 5036 -367 157 s 31 2484 1098 108 c 9 5036 -295 158 s 32 2412 1098 109 c 8 5036 -223 159 s 33 2340 1098 110 c 7 5036 -151 160 s 34 2268 1098 111 c 6 5036 -79 161 s 35 2196 1098 112 c 5 5036 -7 162 s 36 2124 1098 113 c 4 5036 65 163 s 37 2052 1098 114 c 3 5036 137 164 s 38 1980 1098 115 c 2 5036 209 165 s 39 1908 1098 116 c 1 5036 281 166 s 40 1836 1098 117 c 0 5036 353 167 s 41 1764 1098 118 coms 5036 425 168 s 42 1692 1098 119 dummy 26 5036 569 169 s 43 1620 1098 120 dummy 27 5036 641 170 s 44 1548 1098 121 dummy 28 5036 713 171 s 45 1476 1098 122 dummy 29 5036 785 172 s 46 1404 1098 123 dummy 30 5036 857 173 s 47 1332 1098 124 dummy 31 5036 929 174 s 48 1260 1098 125 ali_b1 5036 1089 175 s 49 1188 1098 126 s 0 4716 1098 176 s 50 1116 1098 127 s 1 4644 1098 177 s 51 1044 1098 128 s 2 4572 1098 178 s 52 972 1098 129 s 3 4500 1098 179 s 53 900 1098 130 s 4 4428 1098 180 s 54 828 1098 131 s 5 4356 1098 181 s 55 756 1098 132 s 6 4284 1098 182 s 56 684 1098 133 s 7 4212 1098 183 s 57 612 1098 134 s 8 4140 1098 184 s 58 540 1098 135 s 9 4068 1098 185 s 59 468 1098 136 s 10 3996 1098 186 s 60 396 1098 137 s 11 3924 1098 187 s 61 324 1098 138 s 12 3852 1098 188 s 62 252 1098 139 s 13 3780 1098 189 s 63 180 1098 140 s 14 3708 1098 190 s 64 108 1098 141 s 15 3636 1098 191 s 65 36 1098 142 s 16 3564 1098 192 s 66 -36 1098 143 s 17 3492 1098 193 s 67 -108 1098 144 s 18 3420 1098 194 s 68 -180 1098 145 s 19 3348 1098 195 s 69 -252 1098 146 s 20 3276 1098 196 s 70 -324 1098 147 s 21 3204 1098 197 s 71 -396 1098 148 s 22 3132 1098 198 s 72 -468 1098 149 s 23 3060 1098 199 s 73 -540 1098 150 s 24 2988 1098 200 s 74 -612 1098 -5 - NJU6674 pad no. terminal x= m y= m pad no. terminal x= m y= m 201 s 75 -684 1098 251 s 125 -4284 1098 202 s 76 -756 1098 252 s 126 -4356 1098 203 s 77 -828 1098 253 s 127 -4428 1098 204 s 78 -900 1098 254 s 128 -4500 1098 205 s 79 -972 1098 255 s 129 -4572 1098 206 s 80 -1044 1098 256 s 130 -4644 1098 207 s 81 -1116 1098 257 s 131 -4716 1098 208 s 82 -1188 1098 258 ali_b2 -5036 1089 209 s 83 -1260 1098 259 dummy 32 -5036 929 210 s 84 -1332 1098 260 dummy 33 -5036 857 211 s 85 -1404 1098 261 dummy 34 -5036 785 212 s 86 -1476 1098 262 dummy 35 -5036 713 213 s 87 -1548 1098 263 dummy 36 -5036 641 214 s 88 -1620 1098 264 dummy 37 -5036 569 215 s 89 -1692 1098 265 dummy 38 -5036 497 216 s 90 -1764 1098 266 c 19 -5036 425 217 s 91 -1836 1098 267 c 20 -5036 353 218 s 92 -1908 1098 268 c 21 -5036 281 219 s 93 -1980 1098 269 c 22 -5036 209 220 s 94 -2052 1098 270 c 23 -5036 137 221 s 95 -2124 1098 271 c 24 -5036 65 222 s 96 -2196 1098 272 c 25 -5036 -7 223 s 97 -2268 1098 273 c 26 -5036 -79 224 s 98 -2340 1098 274 c 27 -5036 -151 225 s 99 -2412 1098 275 c 28 -5036 -223 226 s 100 -2484 1098 276 c 29 -5036 -295 227 s 101 -2556 1098 277 c 30 -5036 -367 228 s 102 -2628 1098 278 c 31 -5036 -439 229 s 103 -2700 1098 279 c 32 -5036 -511 230 s 104 -2772 1098 280 c 33 -5036 -583 231 s 105 -2844 1098 281 c 34 -5036 -655 232 s 106 -2916 1098 282 c 35 -5036 -727 233 s 107 -2988 1098 283 c 36 -5036 -799 234 s 108 -3060 1098 284 c 37 -5036 -871 235 s 109 -3132 1098 285 coms -5036 -943 236 s 110 -3204 1098 286 ali_a1 -5036 -1098 237 s 111 -3276 1098 238 s 112 -3348 1098 239 s 113 -3420 1098 240 s 114 -3492 1098 241 s 115 -3564 1098 242 s 116 -3636 1098 243 s 117 -3708 1098 244 s 118 -3780 1098 245 s 119 -3852 1098 246 s 120 -3924 1098 247 s 121 -3996 1098 248 s 122 -4068 1098 249 s 123 -4140 1098 250 s 124 -4212 1098 - 6 - NJU6674 block diagram internal bus common drivers shift register c 19 s 131 s 0 segment drivers display data latch 132 bits display data ram 132 x 39 bits column address decoder column address counter 8bit column address register 8bit multiplexer v ss1 v dd 5 v 1 to v 5 common timing generator display timing generator oscillator cl status bf bus holder instruction decoder mpu interface p/s a0 wrb (r/wb) rdb (e) d 0 to d 5 d 6 (scl) d 7 (si) cls internal power circuits c1+ c1- c2+ c2- cs 1 b common drivers shift register c 0 c 18 cs 2 c3- v ss2 vr v rs irs coms c o m s v out sel68 common direction row address decoder line address decoder line counter initial display line page address register i/o buffer resb reset c 37 -7 - NJU6674 terminal description no. symbol i/o description 1 to 15 85 89 to 97 119 to 124 259 to 265 dummy 1 to dummy 38 dummy terminals. these are open terminals electrically. 20,26, 35 to 38, 62 to 63, 76 to 77, 79,84,88 v dd power power supply terminals. 17,23, 39 to 41, 58 to 59, 81,86 v ss1 gnd ground terminal. 42 to 45 v ss2 power reference voltage for voltage booster 60 to 61 v rs i external reference voltage input terminal. lcd driving voltage supplying terminal. when the internal voltage booster is not used, supply each level of lcd driving voltage from outside with following relation. v dd v 1 v 2 v 3 v 4 v 5 v out when the internal power supply is on, the internal circuits generate and supply following lcd bias voltage from v 1 to v 4 terminal. bias v 1 v 2 v 3 v 4 1/5 bias v 5 +4/5 v lcd v 5 +3/5 v lcd v 5 +2/5 v lcd v 5 +1/5 v lcd 1/6 bias v 5 +5/6 v lcd v 5 +4/6 v lcd v 5 +2/6 v lcd v 5 +1/6 v lcd 64,65 66,67 68,69 70,71 72,73 v 1 v 2 v 3 v 4 v 5 power v lcd =v dd -v 5 50,51 52,53 56,57 54,55 48,49 c1+ c1- c2+ c2- c3- o boosted capacitor connecting terminals used for voltage booster. 46,47 v out o voltage booster output terminal. connect the boosted capacitor between this terminal and v ss1 . 74,75 vr i voltage adjust terminal. v 5 level is adjusted by external bleeder resistance connecting between v dd and v 5 terminal.(irs=?l?) irs terminal connect with "h" at the time of built-in resistance used. ?h? , this terminal must connect to "h" or "l". 27 28 29 30 31 32 33 34 d 0 d 1 d 2 d 3 d 4 d 5 d 6 (scl) d 7 (si) i/o p/s="h": tri-state bi-directional data i/o terminal in 8-bit paralle l operation. p/s="l" : serial data input terminal. (d 7 ) serial data clock signal input terminal. (d 6 ) data from si i s loaded at the rising edge of scl and latched as the parallel data at 8th rising edge of scl. 87 irs i internal resistor select terminal ?h?: internal ?l?: external this terminal must connect to "h" or "l". - 8 - NJU6674 no. symbol i/o description connect to the address bus of mpu. the data on the d 0 to d 7 is distinguished between display data and instruction by status of a0. a0 h l discrimination. display data instruction 22 a0 i 21 resb i reset terminal. when the resb terminal goes to ?l?, the initialization i s performed. reset operation is executing during ?l? state of resb. 18 19 cs 1 b cs 2 i chip select terminal. data input/output are available during cs 1 b=?l? and cs 2 =?h?. 25 rdb(e) i -9 - NJU6674 no. symbol i/o description lcd driving signal output terminals. common output terminals :c 0 to c 37 segment output terminals :s 0 to s 131 ? common output terminal the following output voltages are selected by the combination of fr and status of common. scan data fr output voltage h v 5 h l v dd h v 1 117~99 266 to 284 c 0 to c 18 c 19 to c 37 o o l l v 4 power save v dd ? segment output terminal the following output voltages are selected by the combination of fr and data in the ram. output voltage ram data fr normal reverse h v dd v 2 h l v 5 v 3 h v 2 v dd l l v 3 v 5 power save v dd 126 to 257 s 0 to s 131 o 118 285 coms o com output terminals for the indicator. both terminals output the same signal. leave these open if they are not used. 78 test i maker testing terminal. used for maker test (no connections ) - 10 - NJU6674 functional description (1) block circuits description (1-1) busy flag (bf) during internal operation, the lsi is being busy and can?t accept any instructions except ?status read?. the bf data is output through d 7 terminal by the ?status read? instruction. when the cycle time (tcyc) mentioned in the ?ac characteristics? is satisfied, the bf check isn?t required after each instruction, so that mpu processing performance can be improved. (1-2) initial display line register the initial display line register assigns a ddram line address, which corresponds, to com 0 by ?initial display line set? instruction. it is used for not only normal display but also vertical display scrolling and page switching without changing the contents of the ddram. however, the 39 th address for icon display can?t be assigned for initial display line address. (1-3) line counter the line counter provides a ddram line address. it initializes its contents at the switching of frame timing signal (fr), and also counts-up in synchronization with common timing signal. (1-4) column address counter the column address counter is an 8-bit preset counter, which provides a ddram column address, and it is independent of below-mentioned page address register. it will increment (+1) the column address whenever ?display data read? or ?display data write? instructions are issued. however, the counter will be locked when no-existing address above (84)h are addressed. the count-lock will be able to be released by the ?column address set? instruction again. the counter can invert the correspondence between the column address and segment driver direction by means of ?adc set? instruction. (1-5) page address register the page address register provides a ddram page address. the page address ?1 to 3? should be used the d 0 , d 1 , d 2 , d 3 , d 4 , d 5 , d 6 , d 7 are valid. the page address ?4? should be used the only d 0 , d 1 , d 2 , d 3 , d 4 , d 5 are valid. the last page address ?5? should be used for icon display because the only d 0 is valid. (1-6) display data ram (ddram) the ddram contains 5,148-bit, and stores display data, which are 1-to-1 correspondents to lcd panel pixels. when normal display mode, the display data ?1? turns on and ?0? turns off lcd pixels. when inverse display mode, ?1? turns off and ?0? turns on. - 11 - NJU6674 page address (d 2 ,d 1 ,d 0 ) data display pattern line address common driver d 0 00 c 0 d 1 01 c 1 d 2 02 c 2 d 3 03 c 3 d 4 04 c 4 d 5 05 c 5 d 6 06 c 6 0, 0, 0 d 7 page 0 07 c 7 d 0 08 c 8 d 1 09 c 9 d 2 0a c 10 d 3 0b c 11 d 4 0c c 12 d 5 0d c 13 d 6 0e c 14 0, 0, 1 d 7 page 1 0f c 15 d 0 10 c 16 d 1 11 c 17 d 2 12 c 18 d 3 13 c 19 d 4 14 c 20 d 5 15 c 21 d 6 16 c 22 0, 1, 0 d 7 page 2 17 c 23 d 0 18 c 24 d 1 19 c 25 d 2 1a c 26 d 3 1b c 27 d 4 1c c 28 d 5 1d c 29 d 6 1e c 30 0, 1, 1 d 7 page 3 1f c 31 d 0 20 c 32 d 1 21 c 33 d 2 22 c 34 d 3 23 c 35 d 4 24 c 36 1, 0, 0 d 5 page 4 25 c 37 1, 0, 1 d 0 page 5 comm* d 0 =0 00 01 02 03 04 05 82 83 column address(adc) d 0 =1 83 82 81 80 7f 7e 01 00 segment drivers s 0 s 1 s 2 s 3 s 4 s 5 s 130 s 131 *: comm is independent of the ?initial display line set? instruction and always corresponds to the 39 th line. fig.1 display data ram (ddram) map - 12 - NJU6674 (1-7) common direction register the common direction register specifies common driver?s scanning direction. table 1. common drivers pad no. 117 99 284 266 pin name c 0 c 18 c 37 c 19 ?l? com 0 com 18 com 37 com 19 common direction select(d 3 ) ?h? com 37 com 19 com 0 com 18 the duty ratio setting and output assignment register are so controlled to operate independently that duty ratio setting required to corresponding duty ratio for output assignment. (1-8) reset circuit the reset circuit initializes the lsi to the following status by using of the reset signal into the resb terminal. ? reset status using the res terminal: 1. display off 2. normal display (non-inverse display) 3. adc select : normal mode (d 0 =0) 4. power control register clear : d 2 , d 1 , d 0 =?0, 0, 0? 5. serial interface register clear 6. lcd bias select : d 0 =?0?(1/6 bias) 7. entire display off : d 0 =?0? (normal mode) 8. read modify write off 9. initial display line address : 00 h 10. column address : 00 h 11. page address : 0 page 12. common direction register : normal mode (d 3 =0) 13. v 5 level is adjusted by external bleeder resistance : d 2 , d 1 , d 0 =?1, 0, 0? 14. evr mode off and evr register : d 5 , d 4 , d 3 , d 2 , d 1 , d 0 =?1, 0, 0, 0, 0, 0? the resb terminal should be connected to mpu?s reset terminal, and the reset operation should be executed at the same timing of the mpu reset. as described in the ?dc characteristics? , it is necessary to input 10us(min.) or over ?l? level signal into the resb terminal in order to carry out the reset operation. the lsi will return to normal operation after about 1.0us(max.) from the rising edge of the rest signal. in case of using external power supply for lcd driving voltage, the resb terminal is required to be being ?l? level when the external power supply is turned-on. the ?reset? instruction in table.4 can?t be substituted for the reset operation by using of the resb terminal. it executes above-mentioned only 8 to 14 items. - 13 - NJU6674 lcd driving circuits (a) common and segment drivers lcd drivers consist of 38-common drivers, 132-segment divers and 1-icon-common driver. as shown in ?lcd driving waveform?, lcd driving waveforms are generated by the combination of display data, common timing signal and internal fr timing signal. (b) display data latch circuit the display data latch circuit temporally stores 132-bit display data transferred from the ddram in the synchronization with the common timing signal, and then it transfers these stored data to the segment drivers. ?display on/off?, ?inverse display on/off? and ?entire display on/off? instructions control only the contents of this latch circuit, they can?t change the contents of the ddram. in addition, the lcd display isn?t affected by the ddram accesses during its displaying because the data read-out timing from this latch circuit to the segment drivers is independent of accessing timing to the ddram. (c) line counter and latch signal or latch circuits the clock line counter and latch signal to the latch circuits are generated from the internal display clock (cl). the line address of display data ram is renewed synchronizing with display clock (cl). 132bits display data are latched in display latch circuits synchronizing with display clock, and then output to the lcd driving circuits. the display data transfer to the lcd driving circuits is executed independently with ram access by the mpu. (d) display timing generator the display timing generates the timing signal for the display system bay combination of the master clock cl and driving signal fr ( refer to fig.2 ) the frame signal fr and lcd alternative signal generate lcd driving waveform on the two frame alternative driving method. (e) common timing generation the common timing is generated by display clock cl (refer to fig.2) fig.2 waveform of display timing v dd v dd v dd v 1 v 1 v 4 v 2 v 4 v 5 v 5 v 5 v 3 cl (lsi internal signal) fr c 0 c 1 ram data sn 37 38 1 2 3 4 5 6 7 8 36 37 38 1 2 3 4 5 6 7 - 14 - NJU6674 (f) oscillator this is the low power consumption cr oscillator which provides the display clock and voltage converter timing clock. either external or internal oscillator can be selected by setting the cls terminal to ?l? or ?h? as shown in below. cls=?l? : external oscillator cls=?h? : internal oscillator when the internal oscillator is used, the cl terminal fixed to ?h? or ?l?. when the external oscillator is used, the cl terminal into display clock. (g) internal power circuits the internal power circuits are composed of x4 boost voltage converter, output voltage regulator including 64-step evr and voltage followers. the optimum values of the external passive components for the internal power circuits, such as capacitors for v 1 to v 5 terminals and feed back resistors for vr terminal, depend on lcd panel size. therefore, it is necessary to evaluate the actual lcd module with these external components in order to determine the optimum values. each portion of the internal power circuits is controlled by ?power control set? instruction as shown in table.2. in addition, the combination of power supply circuits is described in table.3. table.2 power control set bits portions status d 2 voltage converter 1 :on 0: off d 1 voltage regulator 1 :on 0: off d 0 voltage followers 1 :on 0: off table.3 power supply combinations status d 2 d 1 d 0 voltage converter voltage regulator voltage followers external voltage capacitor terminals using all internal power circuits 1 1 1 on on on v ss2 use using voltage regulator and voltage followers 0 1 1 off on on v out , v ss2 open using voltage followers 0 0 1 off off on v out , v 5 , v ss2 open using only external power supply 0 0 0 off off off v out , v 1 to v 5 open note1) capacitor input terminals: c1+, c1-, c2+, c2-, c3- note2) do not use other combinations except examples in table.3. note3) connect decoupling capacitors on v 1 to v 5 terminals whenever using the voltage followers. - 15 - NJU6674 - power supply applications power control instruction d 2 : boost circuit d 1 : voltage regulator d 0 : voltage follower (1) internal power supply example. (2) internal power supply example. v 5 level is adjusted by internal bleeder v 5 level is adjusted by internal bleeder resistance (irs=?h?) resistance (irs=?l?) all of the internal booster, voltage regulator, all of the internal booster, voltage regulator, voltage follower using. (d 2 ,d 1 ,d 0 ) = (1,1,1) voltage follower using. (d 2 ,d 1 ,d 0 ) = (1,1,1) * :bias capacitors are selected depending on the lcd panel. the evaluation in various display patterns should be experimented in the application. v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v dd v 5 vr + + + + + + c1 - c1 + c3 - c2 + c2 - + + irs v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v dd v 5 vr + + + + + + c1 - c1 + c3 - c2 + c2 - + + irs - 16 - NJU6674 (3) only v out supply from outside example. (4) only v out supply from outside example. v 5 level is adjusted by internal bleeder v 5 level is adjusted by internal bleeder resistance (irs=?h?) resistance (irs=?l?) internal voltage regulator, internal voltage regulator, voltage follower using. voltage follower using. (d 2 ,d 1 ,d 0 ) = (0,1,1) (d 2 ,d 1 ,d 0 ) = (0,1,1) (5) v out and v 5 supply from outside example. (6) external power supply example. internal voltage follower using. all of v 1 to v 5 and v out supply from outside (d 2 ,d 1 ,d 0 ) = (0,0,1) (d 2 ,d 1 ,d 0 ) = (0,0,0) : these switches should be open during the power save mode. : *bias capacitors are selected depending on the lcd panel. the evaluation in various display patterns should be experimented in the application. v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 + + + + v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v dd vr v 5 + + + + + irs v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v dd vr v 5 + + + + + irs - 17 - NJU6674 instruction set the NJU6674 distinguishes the data on the data bus d 7 to d 0 as an instruction by combination of a0, rdb(e), wrb(r/w) signals. the decoding of the instruction and execution performs with only high speed internal timing without relation to the external clock. therefore, no busy flag check required normally. in case of the serial interface, the data inpu t as msb(d 7 ) first serially. table.4 shows the instruction codes of the NJU6674. table.4 instruction table instruction code instruction a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 description (a) display on/off 0 1 0 1 0 1 0 1 1 1 0/1 lcd display on/off d 0 =0:off d 0 =1:on (b) initial display line set 0 1 0 0 1 start address determine the display line of ram to com 0 (c) page address set 0 1 0 1 0 1 1 * page address set the page of dd ram to the page address register column address set (upper 4-bit) 0 1 0 0 0 0 1 higher order culomn address set the higher order 4 bits column address to the reg. (d) column address set (lower 4-bit) 0 1 0 0 0 0 0 lower order culomn address set the lower order 4 bits column address to the reg. (e) status read 0 0(1) 1 status 0 0 0 0 read out the internal status (f) display data write 1 1 0 write data write the data into the display data ram (g) display data read 1 0 1 read data read the data from the display data ram (h) adc select 0 1 0 1 0 1 0 0 0 0 0/1 set the dd ram vs segment d 0 =0:normal d 0 =1:inverse (i) inverse display on/off 0 1 0 1 0 1 0 0 1 1 0/1 inverse the on and off display d 0 =0:normal d 0 =1:inverse (j) entire display on/off 0 1 0 1 0 1 0 0 1 0 0/1 whole display turns on d 0 =0:normal d 0 =1: whole disp. on (k) lcd bias select 0 1 0 1 0 1 0 0 0 1 0/1 set the lcd bias ratio d 0 =0:1/6 d 0 =1:1/5 (l) read modify write 0 1 0 1 1 1 0 0 0 0 0 increment the column address register when writing but no-change when reading (m) end 0 1 0 1 1 1 0 1 1 1 0 release from the read modify write mode (n) reset 0 1 0 1 1 1 0 0 0 1 0 initialize the internal circuits (o) common direction select 0 1 0 1 1 0 0 0/1 * * * select common direction d 3 =0:normal d 3 =1:inverse (p) power control set 0 1 0 0 0 1 0 1 d 2 d 1 d 0 set the status of internal power circuits (q) internal resistor ratio set 0 1 0 0 0 1 0 0 d 2 d 1 d 0 set the status of internal resistor ratio (ra/rb) (r) evr mode set 0 1 0 1 0 0 0 0 0 0 1 set evr mode (s) evr register set 0 1 0 * * setting data set evr register (t) pawer save mode on/off 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 set the power save mode (lcd display off) (u) nop 0 1 0 1 1 1 0 0 0 1 1 (v) reserve (inhibited) 0 0 1 1 0 0 1 * 0 * 1 * 0 * 1 * 1 * 0 * 0 * inhibited command (w) test 0 1 0 1 0 1 0 1 1 1 0/1 inhibited command (*don?t care) - 18 - NJU6674 (2) instruction description (a) display on/off the ?display on/off? instruction is used to control the display on or off without changing the display data in the ddram. all of the com terminals at the time of ?display off? and seg terminals are set to v dd level. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 1 1 1 d d 0: display off 1: display on (b) initial display line set this instruction specifies the ddram line address which corresponds to the com 0 position. by means of repeating this instruction, the initial display line address will be dynamically changed; it means smooth display scrolling will be enabled. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 1 a 5 a 4 a 3 a 2 a 1 a 0 a 5 a 4 a 3 a 2 a 1 a 0 line address (hex) 0 0 : : 1 0 0 : : 0 0 0 : : 0 0 0 : : 1 0 0 : : 0 0 1 : : 1 00 01 : : 25 (c) page address set in order to access to the ddram for writing or reading display data, both ?page address set? and ?column address set? instructions are required before accessing. the last page address ?5? should be used for icon display because the only d 0 is valid. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 1 * a 2 a 1 a 0 (*: don?t care) a 2 a 1 a 0 page 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 2 3 4 5 - 19 - NJU6674 (d) column address set as above-mentioned, in order to access to the ddram for writing or reading display data, it is necessary to execute both ?page address set? and ?column address set? before accessing. the 8-bit column address data will be valid when both upper 4-bit and lower 4-bit data are set into the column address register. once the column address is set, it will automatically increment (+1) whenever the ddram will be accessed, so that the ddram will be able to be continuously accessed without ?column address set? instruction. the column address will stop increment and the page address will not be changed when the last address (83)h is addressed. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 0 1 a 7 a 6 a 5 a 4 upper 4-bit 0 1 0 0 0 0 0 a 3 a 2 a 1 a 0 lower 4-bit a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 column address (hex) 0 0 : : 1 0 0 : : 0 0 0 : : 0 0 0 : : 0 0 0 : : 0 0 0 : : 0 0 0 : : 1 0 1 : : 1 00 01 : : 83 (e) status read this instruction reads out the internal status regarding ?busy flag?, ?adc select?, ?display on/off? and ?reset?. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 1 busy adc on/of f reset 0 0 0 0 busy: when d 7 is ?1?, the lsi is being busy and can?t accept any instructions. adc: it shows the correspondence between the column address and segment drivers. when d 6 is ?0?, the column address (131-n) corresponds to segment driver n. when d 6 is ?1?, the column address (n) corresponds to segment driver n. please be careful that read out data is opposite of ?adc select? instruction data. on/off: it shows display on or off status. when d 5 is ?0?, the lsi is in display-on status. when d 5 is ?1?, the lsi is in display-off status. please be careful that read out data is opposite of ?display on/off? instruction data. reset: it shows reset status. when d 4 is ?0?, the lsi is in normal operation. when d 4 is ?1?, the lsi is during reset operation. (f) display data write this instruction writes display data into the selected column address on the ddram. the column address automatically increments (+1) whenever the display data is written by this instruction, so that this instruction can be continuously issued without ?column address set? instruction. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 1 0 write data - 20 - NJU6674 (g) display data read this instruction reads out the display data stored in the selected column address on the ddram. the column address automatically increments (+1) whenever the display data is read out by this instruction, so that this instruction can be continuously issued without ?column address set? instruction. after the ?column address set? instruction, a dummy read will be required, please refer to the (4-5). in case of using serial interface mode, this instruction can?t be used. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 0 1 read data (h) adc select this instruction selects segment driver direction. the correspondence between the column address and segment driver direction is shown in fig.1. segment driver output order is inverse, when this instruction executes, therefore, the placement NJU6674 against the lcd panel becomes easy. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 0 d d 0: clokwise output(normal) 1: counterclockwise output(inverse) (i) inverse display on/off this instruction inverses the status of turn-on or turn-off of entire lcd pixels. it doesn?t change the contents of the ddram. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 1 d d 0: normal ram data ?1? correspond to ?on? 1: inverse ram data ?0? correspond to ?on? (j) entire display on/off this instruction turns on entire lcd pixels regardless the contents of the ddram. it doesn?t change the contents of ddram. this instruction executed prior to the ?normal or inverse display on/off set? instruction. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 1 0 d d 0: normal display 1: whole display turns on when the ?entire display on? instruction is executed at display off states, the NJU6674 operates in power save mode. (refer ?power save mode?) (k) lcd bias set this instruction selects lcd bias value. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 1 0 0 0 1 d d 0: 1/6 bias 1: 1/5 bias - 21 - NJU6674 (l) read modify write this instruction sets the read modify write controlling the column address increment. in this mode, column address only increments when execute the display data ?write? instruction; but no change when the display data ?read? instruction. this states is continued until the end instruction(m) execution. when the end instruction is executed, the column address goes back to the start address before the execution of this ?read modify write? instruction. this function reduces the load of mpu for repeating display data change of the fixed area. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 0 0 *) in this ?read modify write? mode, out of display data ?read?/?write?, any instructions except ?column address set? can be executed. the sequence of cursor blink display column address goes back to the start address.(*) pa g e address se t finish? set to the start address of cursor display(*) start the read modify write no yes column address se t read modify write dumm y read data read data write the data is ignored dumm y read data read data write dumm y read data read end data write data inverse b y mpu column counter doesn?t increase column counter increase column counter doesn?t increase column counter increase column counter increase end the read modify write column counter doesn?t increase column counter doesn?t increase column counter doesn?t increase - 22 - NJU6674 (m) end the ?end? instruction cancels the read modify write mode and makes the column address return to the initial value just before ?read modify write? is started. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 1 1 1 0 (n) reset this instruction reset the lsi to the following status, however it doesn?t change the contents of the ddram. please be careful that it can?t be substituted for the reset operation by using of the resb terminal. reset status by ?reset? instruction: 1: read modify write off 2: initial display line address : (00) h 3: column address : (00) h 4: page address : (0) page 5: common direction register : normal mode (d 3 =?0?) 6: v 5 level is adjusted by external bleeder resistance (d 2 , d 1 , d 0 =?1, 0, 0?) 7: evr register : (d 5 , d 4 , d 3 , d 2 , d 1 , d 0 =?1, 0, 0, 0, 0, 0?) a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 1 0 0 0 1 0 (o) common driver direction select this instruction selects common driver direction. please refer to (1-7) common driver direction for more detail . a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 1 0 0 d 3 * * * (*: don?t care) d 3 0: normal (c 0 c 37 ) 1: inverse (c 37 c 0 ) column address read modify write n n+1 n+2 n+3 n+m n end return - 23 - NJU6674 (p) power control set this instruction controls the status of internal power circuits. please refer to the (1-9) lcd driving circuits (g) internal power circuits for more detail. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 1 d 2 d 1 d 0 d 2 0: voltage converter off 1: voltage converter on d 1 0: voltage regulator off 1: voltage regulator on d 0 0: voltage followers off 1: voltage followers on note) the internal power supply must be off when external power supply using. * the wait time depends on the c 4 to c 8 , c out capacitors, and v dd and v 5 voltage. therefore it requires the actual evaluation using the lcd module to get the correct time. lcd driving power supply on/off sequences. the sequences below are required when the power supply turns on/off. for the power supply turning on operation after the power-save mode(p), refer the ?power save release? mentioned after. turn on seaquence turn off seaquence ( ? 1) the internal power supply rise time is depending on the condition of the supply voltage, v lcd =v dd -v 5 , external capacitor of booster, and external capacitor connected to v 1 to v 5 . to know the rise time correctly, test by using the actual lcd module. refer to (3-5) ?lcd driving voltage generation circuits?. entire display on display off display off NJU6674 power off power control off or ext. power supply off (wait time *1) e.v.r register set (wait time *1) display on internal resister ratio set power control on or ext. power supply on - 24 - NJU6674 (q) internal resistor ratio set the ?internal resistor ratio set? instruction is used to determine the internal resistor ratio for the voltage regulator. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 0 0 1 0 0 a 2 a 1 a 0 d 2 d 1 d 0 internal resistor ratio(1+rb/ra) internal resistor ratio(1+rb/ra) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.4 minimum : : : : : : maximum (r),(s) evr set (r) evr mode set this instruction sets the lsi into the evr mode, and it is always used by the combination with ?evr register set?. the lsi can?t accept any instructions except the ?evr register set? during the evr set mode. this mode will be released after the ?evr register set? instruction. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 1 0 0 0 0 0 0 1 (s) evr register set this instruction sets 6-bit data into the evr register to determine the output voltage ?v 5 ? of the internal voltage regulator. a0 rdb wrb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 1 0 * * d 5 d 4 d 3 d 2 d 1 d 0 (*: don?t care) d 5 d 4 d 3 d 2 d 1 d 0 v 5 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 0 : : 1 0 1 : : 1 minimum : : : maximum when evr doesn?t use, set the evr register to d 5 , d 4 , d 3 , d 2 , d 1 , d 0 = ?1, 0, 0, 0, 0, 0?. - 25 - NJU6674 (t) power save(complex command) when entire display on at the display off states(inverse order also same), the internal cirsuits goes to the power save mode and the operating curent is dramatically reduced, almost same as the standby current. the internal states in the power save mode is shown as follows; 1: the oscillation circuits and the internal power supply circuits stop the operation. 2: lcd driving is stopped. segment and common drives output v dd level voltage. 3: the display data and the internal operating condition are remained and kept as just before enter the power save mode. 4: all the lcd driving bias voltage(v 1 to v 5 ) is fixed to the v dd level. the power save and its release perform according to the following sequences. power save sequence *1 power save releace sequence *2 *1: in the power save sequence, the power save mode starts after the entire display on command is executed. *2: in the power save release sequence, power save mode releases just after the entire display off instruction. the display on instruction is allowed to execute at any time after the entire display off instruction is completed. *3: the internal power supply rise time depending on the condition of the supply voltage, v lcd =v dd -v 5 , external capactor of booster, and external capacitor connected to v 1 to v 5 . to know the rise time correctly, test by using the actual lcdmodule. *4: lcd driving waveform is output after the exection of the display on instruction execution. *5: in case of the external power supply operation, the external power supply should be turned off before the power save mode and connected to the v dd for fixing the voltage. in this time, v out terminal also shold be made condition like as connection to v ss . (u) nop this instruction is non operation instruction. (v) reserve, (w) test this instruction is used only for manufacturer?s tests. (don?t inhibited command) *4 entire display off (wait time) *3 display on display off entire display on - 26 - NJU6674 (3) internal power supply (3-1) voltage converter the voltage converter generates maximum 4x boosted negative-voltage from the voltage between v dd and v ss2 . the boosted voltage is output from the v out terminal. the internal oscillator is required to be operating when using this converter, because the divided signal provided from the oscillator is used for the internal timing of this circuit. the boosted voltage between v dd and v out must not exceed 10.0v. the voltage converter requires external capacitors for boosting as shown in below. the boosted voltage and v dd , v ss2 2x boost 3x boost 4x boost example for connecting the capacitors 4x boost 3x boost 2x boost + + + v ss2 c1- c1+ c3- c2+ c2- v out + + + v ss2 c1- c1+ c3- c2+ c2- v out + + v ss2 c1- c1 + c3- c2+ c2- v out v dd =+3v v ss2 =0v v out =-3v v out =-6v v out =-7.5v v dd =+2.5v - 27 - NJU6674 (3-2) contrast adjustment by the evr function the evr selects the v reg voltage out of following 64 conditions by setting 6-bit data into the evr register. when the evr function, v reg is controlled, and the lcd display contrast is adjusted. the evr controls the voltage of v reg bay instruction and change the voltage of v 5 . a step with evr is set like table shown below. n evr register v reg [v] v 5 63 00 h (0,0,0,0,0,0) (99/162)(v dd -v rs ) minimum 62 01 h (0,0,0,0,0,1) (100/162)(v dd -v rs ) : 61 02 h (0,0,0,0,1,0) (101/162)(v dd -v rs ) : : : : : : : : : : : : : : : : 2 3d h (1,1,1,1,0,1) (160/162)(v dd -v rs ) : 1 3e h (1,1,1,1,1,0) (161/162)(v dd -v rs ) : 0 3f h (1,1,1,1,1,1) (162/162)(v dd -v rs ) maximum * : in use of the evr function, the voltage adjustment circuit must turn on by the power control instruction. (3-3) setting for internal resistor ratio either external or internal feedback resistors can be selected by setting the irs terminal to ?0? or?1?. the internal resistor ratio selects 8 conditions of the feedback resistor ratio(1+rb/ra).the feed back resistor ratio(1+rb/ra) changing 3-bit data into the internal resistor ratio register. irs ra, rb 0 external resistors 1 internal resistors internal resistor ratio register: (reference) d 2 d 1 d 0 (1+rb/ra) 0 0 0 3.0 0 0 1 3.5 0 1 0 4.0 0 1 1 4.5 1 0 0 5.0 1 0 1 5.5 1 1 0 6.0 1 1 1 6.4 - 28 - NJU6674 (3-4) voltage adjust circuit the boosted voltage of v out outputs v 5 for v lcd driving through the voltage adjust circuit. this circuit is composed of high the v rs , 64-level evr and internal feedback resistor. (a) using internal resistor ratio function (irs=?1?) the lcd driving volatge v 5 is determined in accordance with the setting for the evr and the internal resistor ratio instruction. the output voltage of v 5 adjusted by changing with in the v 5 >v out . the output voltage is caluculated by the following formula. v 5 =(1+rb/ra)v ev =(1+(rb/ra))(n/162)v reg (a-1) v reg : external constant voltage (v rs ) n : evr value fig-3-a voltage adjust circuit v dd v 5 ra rb (evr) v rs v dd v reg v ev - 29 - NJU6674 (b) using external ra and rb resistors in case that the external feedback resistors (ra, rb) are used by setting the irs terminal to ?0?, these external resistors are required to be placed between the v dd and v r and between the v r and v 5 terminals. the lcd driving voltage v 5 is determined in accordance with the setting for the evr and the external resistor ratio. the output voltage of v 5 adjusted by changing the ra and rb within the v 5 >v out . the output voltage is caluculated by the following formula. v 5 =(1+(rb?/ra?))v ev =(1+(rb?/ra?))(1-(n/162))v reg (b-1) fig-3-b voltage adjust circuit < designe example for r1 and r2 / reference > condition : ta=25 c, n=31, v reg =-2.1v, evr=1f h , v 5 =(1+(rb/ra))(n/162)v reg -7=(1+(rb?/ra?))(1-(31/162) (-2.1) (b-2) determined by the current flown between v dd -v 5 / 5ua. ra?+rb?=1.4m ? (b-3) ra and rb caluculated by above conditions and the formula of (b-2, b-3) to mentioned below; rb?/ra?=3.12 ra=340k ? rb=1060k ? the adjustable v 5 range and step voltage table shown below. v 5 min. typ. max. unit adjustable range -8.6 (63 step) -7.0 (32 step) -5.3(0 step) [v] step voltage 52 [mv] v dd v 5 ra? rb? (evr) v rs v dd v reg v ev - 30 - NJU6674 (3-5) lcd driving voltage generation circuits the lcd driving bias voltage of v 1 ,v 2 ,v 3 ,v 4 are generated by dividing the v 5 voltage with the internal bleeder resistance and is supplied to the lcd driving circuits after the impedence conversion by the voltage follower. the external capacitors to v 1 to v 5 for bias voltage stabilization may be removed in use of small size lcd panel. the equivalent load of lcd panel may be changed depending on display patterns. therefore, it require display quality check on various display patterns actually without external capacitors. if the display quality is not so good, external capacitors should connects as show in fig. 4. (if no need external capacitors as result of experiment, the application patterns (wiring) should be prepared for recovery.) using the internal power supply using the external power supply fig.4 reference set up value v lcd =v dd -v 5 =5.0 to 9.0v ? 1 short wiring or sealed wiring to the vr terminal is required due to the high impedance of vr terminal. ? 2 following connection of v out is required when external power supply using. when v ss >v 5 , v out =v 5 when v ss v 5 , v out =v ss ? 3 bias capacitors are selected depending on the lcd panel. the evaluation in various display patterns should be experimented in the application c out 1.0 f c1, c2, c3 1.0 f c4 to c7 0.1 to 0.47 f r 1 264k ? r 2 211k ? r 3 925k ? irs v dd r3 r2 r1 v ss2 v out c3- c1+ c1- c2+ c2- v dd vr v 2 v 1 v 3 v 4 v 5 v rs + c4 c5 c6 c7 c8 + + + + c out c1 c3 c2 + + v ss1 v ss1 v 5 . . irs v ss1 v dd external voltage generator v dd or v ss1 v ss2 v out c3- c1+ c1- c2+ c2- v dd v 2 v 1 v 3 v 4 v 5 v rs v 5 vr - 31 - NJU6674 (4) mpu interface (4-1) interface type selection NJU6674 interfaces with mpu by 8-bit bi-directional data bus (d 7 to d 0 ) or serial (si:d 7 ). the 8 bit parallel or serial interface is determined by a condition of the p/s terminal connecting to ?h? or ?l? level as shown in table 5. in case of the serial interface, status and ram data read out operation is impossible. table 5 p/s i/f type cs 1 b cs 2 a0 rdb wrb sel68 d 7 d 6 d 5 - d 0 h parallel cs 1 b cs 2 a0 rdb wrb sel68 d 7 d 6 d 5 - d 0 l serial cs 1 b cs 2 a0 - - - si scl hi-z ?hi-z? mark: hi-impedance "-" mark: fix to "h"or "l" (4-2) parallel interface the NJU6674 interfaces the 68- or 80-type mpu directly if the parallel interface (p/s=?h? is selected. the 68-type or 80-type mpu is selected by connecting the sel68 terminal to ?h? or ?l? as shown in table 6. table 6 sel68 type cs 1 b cs 2 a0 rdb wrb d 7 - d 0 h 68-type mpu cs 1 b cs 2 a0 e r/wb d 7 - d 0 l 80-type mpu cs 1 b cs 2 a0 rdb wrb d 7 - d 0 (4-3) discrimination of data bus signal the NJU6674 discriminates the mean of signal on the data bus by the combination of a0, e, r/wb, and (rdb, wrb) signals as shown in table 7. table 7 common 68 type 80 type a0 r/wb rdb wrb function h h l h read display data h l h l write display data l h l h status read l l h l write into the register(instruction) - 32 - NJU6674 (4-4) serial interface.(p/s="l") the serial interface of the NJU6674 consists of the 8-bit shift register and 3-bit counter. in case the chip is selected (cs 1 b=?l?, cs 2 =?h?), the input to d 7 (si) and d 6 (scl) becomes available, and in case that the chip isn?t selected, the shift register and the counter are reset to the initial condition. the data input from the terminal(si) is msb first like as the order of d 7 , d 6 ,------ d 0 , by a serial interface, it is entered into with rise edge of serial clock(scl). the data converted into parallel data of 8-bit with the rise edge of 8th serial clock and processed. it discriminates display data or instructions by a0 input terminal. a0 is read with rise edge of (8 x n)th of serial clock (scl), it is recognized display data by a0=?h? and instruction by a0=?l? a0 input is read in the rise edge of (8 x n)th of serial clock (scl) after chip select and distinguished. however,in case of resb=?h? to ?l? or cs 1 b=?l? to ?h? and cs 2 =?h? to ?l? with trasfered data does not fill 8 bit, attention is necessary because it will processed as there was command input. always, input the data of (8 x n) style. the scl signal must be careful of the termination reflection by the wiring length and the external noise and confirmation by the actual machine is recommended by it. fig.5 d 6 d 0 d 1 d 7 10 cs 1 b, cs 2 si scl a0 d 6 1 d 7 2 d 4 d 5 34 7 8 9 - 33 - NJU6674 (4-5) access to the display data ram and internal register. the NJU6674 transfers data to the mpu through the bus holder with the internal data bus. in case of reading out the display data contents in the dd ram, the data which was read in the first data read cycle (= the dummy read ) is memorized in the bus holder. then the data is read out to the system bus from the bus holder in the next data read cycle. also, in case that the mpu writes into dd ram, the data is temporarily stored in the bus holder and is then written into dd ram by the next data write cycle. therefore, the limitation of the access to NJU6674 from mpu side is not access time (t acc , t ds ) of display data ram and the cycle time becomes dominant. with this, speed-up of the data transfer with the mpu becomes possible. in case of cycle time isn?t met, the mpu inserts nop operation only and becomes an equivalent to an execution of wait operation on the satisfy condition in mpu. when setting an address, the data of the specified address isn?t output immediately by the read operation after setting an address, and the data of the specified address is output at the 2nd data read operation. therefore, the dummy read is always necessary once after the address set and the write cycle. (see fig. 6) the example of read modify write operation is mentioned in (3)instruction -l)the sequence of inverse display. write operation read operation fig.6 (4-6) chip select cs 1 b, cs 2 is chip select terminal. in case of cs 1 b="l" and cs 2 ="h". the interface with mpu is available. in case of cs 1 b=?h? or cs 2 =?l?, the d 0 to d 7 are high impedance and a0, rdb, wrb, si and scl inputs are ignored. if the serial interface is selected when cs 1 b=?h? or cs 2 =?l? the shift register and counter are reset. however, the reset is always operated in any conditions of cs 1 b, cs 2 . bus holder wrb mpu timing internal wrb data n n+1 n+2 n+3 n n+1 n+2 n+3 bus holder wrb timing internal n n+1 n+2 n n+1 n+2 n column address rdb data read n+1 n n n n+1 address set n dummy read data read n wrb data rdb mpu - 34 - NJU6674 absolute maximum ratings parameter symbol ratings unit -0.3 to +7.0 supply voltage(1) v dd -0.3 to +3.6(used tripler) v supply voltage(2) v ss2 -7.0 to +0.3 -3.6 to +0.3(used tripler) v supply voltage(3) v 5 , v out v dd -11.0 to v dd +0.3 v supply voltage(4) v 1 ,v 2 ,v 3 ,v 4 v 5 to v dd +0.3 v supply voltage(5) v rs -7.0 to +0.3 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -40 to +85 c strage temperature t stg -55 to +125 c note 1) all voltage values are specified as v ss1 =0v. note 2) the relation of v dd > v 1 > v 2 > v 3 > v 4 > v 5 >v out ; v dd >v ss1 > v out must be maintained. in case of inputting external lcd driving voltage , the lcd drive voltage should start supplying to NJU6674 at the mean time of turning on v dd power supply or after turned on v dd. in use of the voltage boost circuit, the condition that the supply voltage: 11.0v> v dd -v out is necessary. note 3) if the lsi are used on condition beyond the absolute maximum rating, the lsi may be destroyed. using lsi within electrical characteristics is strongly recommended for normal operation. use beyond the erectric characteristics conditions will cause malfunction and poor reliability. note 4) decoupling capacitor should be connected between v dd and v ss1 due to the stabilized operation for the voltage converter. v dd v ss v 5 v dd - 35 - NJU6674 dc electrical characteristics (v dd =2.4v to 3.3v, v ss =0v, ta=-20 to 75 c) parameter symbol conditions min typ max unit note operating voltage (1) v dd 2.4 3.3 v 1 operating voltage (2) v ss v dd -3.3 v dd -2.4 v recommend v dd -10.0 v dd -5.0 available v 5 v dd -10.0 available v 1 ,v 2 v dd -0.4xv 5 v dd operating voltage (3) available v 3 ,v 4 v lcd =v dd -v 5 v 5 v dd -0.6xv 5 v ?h? level input voltage v ihc 0.8 x v dd v dd ?l? level input voltage v ilc a0, d 0 to d 7 , rdb, wrb, resb, cs 1 b, cs 2 , p/s, sel68 te r m i n a l v ss 0.2 x v dd v ?h? level output voltage v ohc i oh =-0.5ma 0.8 x v dd v dd ?l? level output voltage v olc d 0 to d 7 te r m i n a l i ol = 0.5ma v ss 0.2 x v dd v i li all input terminals -1.0 1.0 input leagage current i lo d 0 to d 7 terminals, hi-z state -3.0 3.0 a driver on-resistance r on ta=25 c, v lcd =8.0v 3.0 4.5 k ? 2 stand-by current i ddq during power save mode 0.01 5.0 a 3 input terminal capacitance c in ta=25 c 10.0 pf 4 oscillation frequency f osc v dd = 3.0v ta =25 c 10.2 12.5 14.8 khz reset time t r resb terminal 1.0 s 5 reset ?l? level pulse width t rw 10.0 s 6 v dd1 3-times boost 2.4 3.3 v dd2 4-times boost 2.4 2.5 v 7 input voltage v rs v dd -5.0 v dd -2.4 v output voltage v out1 4-times boost, v dd =2.5v -10.0 -9.5 v on-resistance r tri 3-times boost, v dd =3.0v, c out =1.0 f 1600 2600 ? a djustment range lcd driving voltage v out2 voltage boost operation off v dd -10.0v v dd -5.0v v voltage follower v 5 voltage adjustment circuit ?off? v dd -10.0v v dd -5.0v v 8 int. resistor ratio intr v dd =3.0v, v rs =v dd -2.4v, evr=00 h ,v out =v dd -10.0v v 5 =no load ;ta =25 c 3.0 % 9 i ddq1 power save mode 0.01 5 a i out1 51 85 a operating current i out2 v dd =3.0v, v lcd =5v, no access com/seg terminals non connect display checkerd pattern 12 20 a 10 note 1) although the NJU6674 can operate in wide range of the operating voltage, it shall not be guaranteed in a sudden voltage fluctuation during the access with mpu. note 2) r on is the resistance values in supplying 0.1v voltage-difference beteen power supply terminals (v 1 ,v 2 ,v 3 ,v 4 ) and each output terminals (common/ segment). this is specified within the range of operating voltage(2). note 3) apply no access from mpu. note 4) apply a0, d 0 to d 7 , rdb, wrb, cs 1 b, cs 2 , resb, p/s, cl terminals. note 5) t r ( reset time ) refers to the reset completion time of the internal circuits from the rise edge of the resb signal. note 6) apply minimum pulse width of the resb signal. to reset, the ?l? pulse over t rw shall be input. note 7) apply to the v dd when using 4-times boost. note 8) the voltage adjustment circuit controls v 5 within the range of the voltage follower operating voltage. note 9) intr : the calculation of (v lcd (ideal)* 1 -(v lcd (real))/v lcd (ideal)) x100% * 1 v lcd (ideal)=nx(1-63/162)x2.4 (n:selected by the ?internal resistor ratio? ) voltage booster - 36 - NJU6674 note10) each operating current shall be defined as being measured in the following condition. power control operating condition symbol d 2 d 1 d 0 voltage converter voltage regulator voltage follower external voltage supply (input terminal) i dd1 1 1 1 validity validity validity use(v ss2 ) i dd2 0 0 0 invalidity invalidity invalidity use(v out , v 1 to v 5 ) :i dd1 :i dd2 fig.7 measurment block diagram + + + v dd v 5 vr v out c1- c1+ c 2 + c3- c2- v ss1 NJU6674 1m ? 500k ? 1.6m ? 1.0 ? 10k ? 10k ? 10k ? 10k ? v dd cls cl v dd a 3v v ss2 v dd - 37 - NJU6674 bus timing characteristics ? read and write characteristics (80 type mpu) (v dd =2.7v to 3.3v, ta=-20 to 75 c) parameter terminal symbol condition min. typ max. unit address hold time t ah8 0 address set up time t aw 8 a0, cs 1 b, cs 2 0 system cycle time t cyc8 300 control ?l? pulse width (write) t ccl(w) 60 control ?l? pulse width (read) t ccl(r) 120 control ?h? pulse width t cch wrb, rdb 60 data set up time t ds8 40 data set up time t dh8 25 rd access time t acc8 140 output disable time t oh8 d 0 to d 7 cl=100pf 10 100 input signal rising, falling edge t r , t f cs 1 b, cs 2 , wrb, rdb a0, d 0 to d 7 15 ns ? *:all timing based on 20% and 80% of v dd voltage level. t cyc8 t f t r t aw 8 t ah8 t ccl t cch t ds8 t dh8 t acc8 t oh8 d 0 to d 7 (write) a0, cs 1 b, cs 2 wrb, rdb d 0 to d 7 (read) - 38 - NJU6674 read and write characteristics (68 type mpu) (v dd =2.7v to 3.3v, ta=-20 to 75 c) parameter symbol terminal condition min typ max unit address hold time t ah6 0 address set up time t aw 6 a0, cs 1 b cs 2 , r/wb 0 system cycle time t cyc6 e 300 write 120 enable ?h? pulse width (read) read t ewh e 60 write 60 enable ?l? pulse width (read) read t ewl e 60 data set up time t ds6 40 data hold time t dh6 25 rd access time t acc6 140 output disable time t oh6 d 0 to d 7 cl=100pf 10 100 input signal rising, falling edge t r , t f e, r/wb, a0, d 0 to d 7 15 ns *:all timing based on 20% and 80% of v dd voltage level. *:t cyc6 shows the cycle of thee signal in active cs 1 b and cs 2 . e t c y c6 t ewh t aw 6 t ah6 t ds6 t dh6 t acc6 t oh6 t r t f t ewl r/wb d 0 ~d 7 ( write ) d 0 ~d 7 ( read ) a0, cs 1 b, cs 2 - 39 - NJU6674 write characteristics (serial interface) (v dd =2.7v to 3.3v, ta=-20 to 75 c) parameter symbol terminal condition min typ max unit serial clock cycle t scyc 250 scl ?h? pulse width t shw 100 scl ?l? pulse width t slw scl 100 address set up time t sas 150 address hold time t sah a0 150 data set up time t sds 100 data hold time t sdh si 100 t css 150 cs-scl time t csh cs 1 b, cs 2 150 input signal rising, falling edge t f , t r cs 1 b, cs 2 scl, si, a0 15 ns *:all timing based on 20% and 80% of v dd voltage level. cs 1 b, cs 2 a0 scl si t css t csh t sas t sah t scyc t slw t shw t f t r t sdh t sds - 40 - NJU6674 lcd driving waveform v 5 v 4 v 3 v 2 v 1 v dd -v 1 -v 2 -v 3 -v 4 -v 5 -v 1 -v 2 -v 3 -v 4 -v 5 v 5 v 4 v 3 v 2 v 1 v dd c 5 c 4 c 3 c 2 c 1 c 0 c 15 c 7 c 6 c 13 c 12 c 11 c 10 c 9 c 8 c 14 s 3 s 4 s 2 s 1 s 0 fr c 1 c 0 ~s 1 c 0 ~s 0 s 1 s 0 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 v dd v 1 v 2 v 3 v 4 v 5 c 0 c 2 v dd v 1 v 2 v 3 v 4 v 5 v dd v ss 1 2 3 4 37 1 2 3 4 5 0 0 38 37 38 - 41 - NJU6674 application circuit ? (1) microprocessor interface example the NJU6674 interfaces to 80 type or 68 type mpu directly. and the serial interface also communicate with mpu. * : c86 terminal must be fixed v dd or v ss . 80 type mpu 68 type mpu serial interface reset cpu decoder NJU6674 v cc iorq d 0 ~d 7 gnd a 0 a1~a7 rd wr res sel68 p/s d 0 ~d 7 a 0 cs 1 b rdb wrb resb v dd v ss v dd cs 2 v dd decoder cpu NJU6674 v cc vm a gnd a 1~a15 e r/w res a 0 d 0 ~d 7 sel68 p/s d 0 ~d 7 a 0 e r/wb resb v dd v ss reset v dd cs 1 b cs 2 decoder cpu sel68 v cc gnd a 1~a7 res a 0 port 1 port 2 NJU6674 p/s d 7 ( si ) a 0 resb v dd v ss d 6 ( scl ) reset cs 1 b cs 2 - 42 - NJU6674 memo [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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